$ dmesg | grep -i boot

Hardware

What is it?

A cheat sheet on what a chip does between power-on and the OS: the TF-A secure boot chain on Arm, the hardware it relies on and how common chips compare, how PCs do the same with BIOS and UEFI, how the kernel boots, and how secure boot differs from measured boot.

// power-on --> chain of trust

Anatomy of a secure boot

The Trusted Firmware-A (TF-A) cold boot, from the reset vector in ROM to the OS: BL1 verifies BL2, then BL2 verifies every BL3x image. BL stands for Boot Loader stage.

TF-A secure boot chain, the hardware it uses, and real chips that run itOn the left, a list of real chips and the boot stages they run, with TF-A stages highlighted. In the middle, cards for the CPU, PLL, watchdog, boot ROM, OTP fuses, crypto engine, Trusted SRAM, flash and DRAM, each with an arrow to the boot stage it serves. On the right, the Reset, BL1, BL2, BL31, BL32, BL33 spine. A verification-failure branch halts the SoC, a dashed line marks the secure/normal world boundary, and the operating system starts once BL33 runs.This chain on real chipsHardware it relies onBoot execution chainTF-A stagevendor or other firmwareArm Juno / FVPBL1 --> BL2 --> BL31 --> OP-TEE --> U-BootST STM32MP25ROM --> BL2 --> BL31 --> OP-TEE --> U-BootRenesas R-Car Gen3ROM --> BL2 --> BL31 --> OP-TEE --> U-BootNXP LayerscapeROM --> BL2 --> BL31 --> OP-TEE --> U-BootST STM32MP15ROM --> BL2 --> OP-TEE --> U-BootNXP i.MX 8MROM --> SPL --> BL31 --> U-BootMost SoCs replace BL1 with a vendor boot ROM that verifies the nextstage. TF-A's BL1 also runs, from flash, on Raspberry Pi 3 and HiKey.Resetpower-on1BL1Trusted ROM, EL3Brings up theplatform, thenloads, thenverifies BL2.2BL2SRAM, S-EL1 or EL3Inits DRAM, locksTrustZone, loadsand verifies theBL3x images.3BL31EL3 runtime4BL32optional5BL33DRAM, EL2/EL16CPU clusterArm cores; run every stage.PLLMultiplies the crystal frequency.WatchdogResets the SoC if boot hangs.Boot ROMImmutable first code; root of trust.OTP / eFusesBurned-in root-key hash + config.Crypto engineOptional signature accelerator.Trusted SRAMBL2 and BL31 run here; BL32 may too.Flash storage (off-die)Board chip; holds the FIP images.DRAM (off-die)Board memory; BL33 and OS run here.Verification failedAny BL check fails: halt or recover.↑ Secure world (EL3 / Secure-EL1)↓ Normal world (EL2 / EL1)Operating system, normal world (loaded, and ideally verified, by BL33)OS kerneltakes controlMount FSfiles appearinit / systemdstarts servicesShell / scriptsbash, python…
Numbered boxes are boot stages; coloured cards are hardware, with an arrow to the stage that uses each one. Chip names link to their TF-A platform pages and are compared in the table below.

Step by step

  1. 0

    Always-on hardware. The CPU, Trusted ROM and on-chip Trusted SRAM are not steps: ROM holds the first code, and SRAM is where BL1's data, BL2 and BL31 run.

  2. 1

    Reset. The primary core leaves reset at the reset vector in Trusted ROM; the other cores wait until the OS starts them through BL31 (PSCI CPU_ON).

  3. 2

    BL1, Trusted ROM (EL3). Immutable code sets up the exception vectors, the watchdog, the console and the MMU, copies BL2 into Trusted SRAM, then verifies that copy against the root-key hash in OTP, in software or with a crypto engine. Checking the copy, not the flash, ensures the verified bytes are the ones that run. With measured boot it also hashes BL2 into the TPM; BL1 is the root of trust for measurement, so nothing measures BL1 itself.

  4. 3

    BL2, Trusted Boot Firmware (Secure-EL1 or EL3). Initialises DRAM on most real SoCs, programs the TrustZone controller to split memory and peripherals into secure and non-secure, then loads and verifies BL31, BL32 and BL33 from the Firmware Image Package (FIP) in flash. It runs at EL3 when a vendor boot ROM loads it directly, as on the vendor chips below. With measured boot it also measures each image it loads and passes the event log on to BL33 and the OS.

  5. 4

    BL31, EL3 runtime. The resident secure monitor: sets up the interrupt controller and PSCI power management, and handles Secure Monitor Calls (SMC) from the normal world for the life of the system.

  6. 5

    BL32, Trusted OS (Secure-EL1, optional). A Trusted OS such as OP-TEE, reached through BL31 and usually running in secure DRAM. On AArch32 there is no BL31 and BL32 is also the monitor.

  7. 6

    BL33, Non-trusted firmware (EL2/EL1). The first non-secure code, usually U-Boot or UEFI, running from DRAM; it boots the OS. TF-A's chain of trust ends here: BL33 must verify the kernel itself (signed FIT images or UEFI Secure Boot).

Details vary by platform. In hardware, the chain can still be bypassed through an open JTAG/SWD debug port, unprogrammed secure-boot fuses, or bugs in the ROM's USB/UART download modes, which boot-strap pins can select (as in Fusée Gelée). Fault injection is behind most of the breaks in the table below.

// under the microscope

Secure boot hardware on real dies

Neither chip runs TF-A, but their delayered dies show the blocks a boot relies on: boot ROM, OTP fuses and SRAM on the RP2350, flash and SRAM on the STM32L431.

OTP fusesSRAMSRAMBoot ROMPLLs
Raspberry Pi RP2350 (Cortex-M33). The boot ROM checks a signed image from external flash against a key hash in the OTP fuses; the cores sit in the unlabelled logic. Outlines from Aedan Cullen's 38C3 talk annotation. Photo: Aedan Cullen, CC BY 4.0.
Delayered STM32L431 die with Flash 1, Flash 2, the flash high-voltage block, SRAM1, SRAM2, small SRAMs A to D and a large-cell library region outlined in red
ST STM32L431 (Cortex-M4). No secure boot in ROM: just a factory bootloader in a system-memory region inside the flash. The uniform area is the logic, the irregular south edge is analog. Photo and annotations: Andrew Zonenberg's teardown (archived), CC BY-SA 4.0.

// who verifies what

Common chips compared

ChipUsed inCPUBoot ROM verifiesRoot key inTrustZoneTF-APublic break
Arm Juno / FVPJuno key storage, TF-A build optionsArm's reference development board, FVP software modelCortex-A72 or A57 (+ A53)No vendor ROM: TF-A BL1 (in flash) verifies BL2, RSA or ECDSARead-only registers (fixed key hash; no OTP)YesBL1, BL2, BL31 (full chain)none
ST STM32MP25ST wiki, TF-ADigi ConnectCore MP25 industrial edge-AI moduleCortex-A35 (+ M33)TF-A BL2, ECDSA (P-256 / Brainpool)OTP (key-table hash)YesBL2, BL31none
Renesas R-Car Gen3Renesas, TF-AToyota / Lexus multimedia (Lexus NX, 2021), Parrot Faurecia cockpitCortex-A57 and/or A53 (+ R7)TF-A BL2, RSA certificatesFuses (customer's root-key hash, programmed by Renesas)YesBL2, BL31none
NXP Layerscape LX2160ATF-A, TF-A secure bootSolidRun HoneyComb LX2 Arm workstation16× Cortex-A72TF-A BL2, RSA (CSF header)Fuses (SRK hash)YesBL2, BL31none
ST STM32MP15ST wiki, TF-AKontron industrial / IoT module, Seeed ODYSSEY moduleCortex-A7 (+ M4)TF-A BL2, ECDSA (P-256 / Brainpool)OTP (key hash)YesBL2none
NXP i.MX 8MU-Boot HABv4, TF-AGoogle Coral Dev Board, Purism Librem 5 phoneCortex-A53 (+ M4 or M7)U-Boot SPL, RSA (HABv4)eFuses (SRK hash)YesBL31none
NVIDIA Tegra X1NVIDIA, 34C3 talk, TF-A commitNintendo Switch (own secure monitor, not TF-A), NVIDIA Shield TV (2015, 2017), Jetson NanoCortex-A57 (+ A53)BCT + bootloader, RSA or AES-CMAC; ROM runs on an ARM7 boot CPUFuses (RSA key hash, or AES Secure Boot Key)YesBL31 (upstream port deprecated in 2026)Fusée Gelée (2018): USB bug in the boot ROM, unpatchable on shipped chips
Raspberry Pi 5 (BCM2712)Pi secure boot, TF-ARaspberry Pi 5, Pi 500, Compute Module 5Cortex-A76Bootloader, RSA-2048, signed by Raspberry Pi and counter-signed by the customerOTP (customer key hash)In the cores, but no secure memory controllerMinimal BL31, not securenone
Raspberry Pi RP2350Pi white paperRaspberry Pi Pico 2Cortex-M33 (+ Hazard3 RISC-V)Signed image, ECDSA secp256k1 + SHA-256OTP (key hash)TrustZone-MNoneOTP power glitch (Aedan Cullen); voltage and laser fault injection; FIB readout of the OTP (IOActive)
ST STM32L431X-CUBE-SBSFUHermetis LoRa air-quality sensor, Andrew Zonenberg's lab hardwareCortex-M4Nothing; ST's X-CUBE-SBSFU adds a software secure boot in flashnoneNoNonenone
Espressif ESP32EspressifShelly Plus 1 smart relayXtensa LX6 (not Arm)Bootloader, AES-based digest (Secure Boot v1); v3 silicon adds RSA-3072 (Secure Boot v2)eFuses (AES key for v1, RSA key hash for v2)NoNoneFault injection skips the Secure Boot check (CVE-2019-15894); Voltage glitching read the eFuse keys (2019); CVE-2019-17391 advisory; One EM glitch via the ROM's UART download mode (Raelize, CVE-2020-13629)

Entries link to their sources; technical columns are sourced under each chip name. “Used in” lists examples; “none” means none known or not applicable.

// BL33 --> firmware you know

BIOS and UEFI

TF-A's chain ends at BL33, which is often a UEFI firmware: the same interface a PC uses to boot. A PC has no TF-A. Intel Boot Guard or AMD's Platform Secure Boot plays the boot ROM's role, and the UEFI firmware itself does BL2's job. Before UEFI, PCs booted with a BIOS, which verified nothing.

The same five boot roles on an Arm SoC with TF-A, a PC with UEFI, and a PC with a legacy BIOSThree rows of five boxes. Columns: root of trust, early init and DRAM, drivers and boot menu, OS loader, kernel. Arm with TF-A: boot ROM or BL1, BL2, BL33 running UEFI or U-Boot, an OS loader, the kernel. PC with UEFI: Intel Boot Guard or AMD Platform Secure Boot, SEC and PEI, DXE and BDS, shim and GRUB or the Windows Boot Manager, the kernel. In both rows each stage verifies the next. PC with BIOS: the reset vector, POST, loading the MBR from sector 0, the MBR and volume boot record, the kernel, with nothing verified.Root of trustEarly init, DRAMDrivers, boot menuOS loaderKernelArm + TF-ASoCs, Arm serversBoot ROM / BL1key hash in OTP;verifies BL2BL2inits DRAM, verifiesBL31, BL32, BL33BL33UEFI (EDK2) or U-Boot;checks the OS loaderOS loaderGRUB, systemd-boot,or none (EFI stub)KernelImage + devicetreeor ACPI tablesPC with UEFIx86 todayBoot Guard / PSBIntel ACM or AMD PSP;OEM key hash in fusesSEC + PEIcache as RAM,then DRAM initDXE + BDSdrivers, BootOrder;Secure Boot: db, dbxOS loadershim + GRUB, orWindows Boot ManagerKernelverifies its modulesand driversPC with BIOSbefore UEFIReset vectorBIOS code in flash,runs uncheckedPOSTinits CPU, DRAMand devicesBoot devicereads sector 0 (MBR)to 0x7C00, real modeMBR + VBR446 bytes of code,chain to GRUB, bootmgrKernelleaves real mode;nothing verified itchecks the next stage's signature first (when enabled)loads it without any check
Sources: Intel Boot Guard key usage, AMD Platform Secure Boot, UEFI PI boot flow, Arm EBBR, MBR (x86).

The x86 root of trust

Before any PC firmware runs, something the OEM cannot change checks it. Intel spreads the check over signed manifests; AMD gives it to a separate security processor. Both are the same idea as BL1 checking BL2 against a key hash in OTP.

Hardware roots of trust on Intel, AMD and ArmThree chains, each stage checking the next before it runs. Intel Boot Guard: the CPU microcode checks the Intel-signed Startup ACM; the ACM checks the OEM Key Manifest against an OEM key hash in chipset fuses, then the Boot Policy Manifest, then the Initial Boot Block against the hash in that manifest; the IBB checks the rest of the firmware. AMD Platform Secure Boot: the AMD Secure Processor boot ROM checks the ASP boot loader, which initialises silicon and DRAM and checks the OEM BIOS against an OEM key bound by fuses. Arm with TF-A: the boot ROM or BL1 checks BL2 against the ROTPK hash in OTP, and BL2 checks the BL3x images.IntelBoot GuardCPUmicrocode, beforeany firmware runsStartup ACMsigned by Intel;runs the checksKey ManifestOEM-signed; listsOEM key hashesBoot PolicyManifest (BPM):holds the IBB hashIBBInitial Boot Block:checks the OBB hashOBBrest of the UEFIfirmwareIntel's keyknown to the CPUOEM key hashchipset fuses (FPF)AMDPSBASP boot ROMon-chip securityprocessor, runs firstASP boot loaderfrom flash; initssilicon and DRAMOEM BIOSthe UEFI firmware,signed by the OEMOEM keybound by PSB fusesArmTF-ABoot ROM / BL1immutable,runs firstBL2inits DRAM,checks BL3xBL31-BL33secure monitor,OS, U-Boot or UEFIROTPK hashOTP fuseschecks the next stage before it runschecked against a key the OEM cannot change later
On Intel, the ACM does every check up to the IBB, then the IBB runs and checks the rest. On AMD, once Platform Secure Boot is enabled, fuses bind the processor to the OEM's signing key for good. Sources: Intel key usage, Boot Guard chain, AMD PRO security.

UEFI in six phases

  1. SEC

    Security. Handles every reset, sets up temporary memory (the CPU cache used as RAM) and is the root of trust of the firmware.

  2. PEI

    Pre-EFI Initialization. Small modules initialise permanent memory (DRAM) and describe it in Hand-Off Blocks for the next phase.

  3. DXE

    Driver Execution Environment. Most of the work: drivers for the chipset, buses, consoles and disks, and the Boot and Runtime Services.

  4. BDS

    Boot Device Selection. Applies the boot policy: reads the BootOrder variables and tries each boot option in turn.

  5. TSL

    Transient System Load. The OS loader runs as an EFI application, still using the Boot Services.

  6. RT

    Runtime. Once the OS takes over, only the Runtime Services remain: variables, clock, capsule firmware updates.

On an Arm board, TF-A has already done the reset and DRAM work, and EDK2 starts as BL33. Embedded boards often run U-Boot instead, which implements the subset of UEFI that Arm's EBBR requires. Secure Boot is optional there. Source: TianoCore PI boot flow, UEFI on U-Boot.

Legacy BIOS vs UEFI

Legacy BIOSUEFI
CPU mode at hand-off16-bit real mode, 1 MiB of addressable memory32- or 64-bit mode (AArch64 on Arm), flat memory
Finds the OS byLoading sector 0 of the boot disk (the MBR) at 0x7C00 and jumping to itRunning the PE/COFF .efi file named by the BootOrder variables, from a FAT EFI System Partition
Disk layoutMBR: 4 primary partitions, 32-bit sector numbers, so 2 TiB with 512-byte sectorsGPT, with 64-bit sector numbers (MBR still allowed)
Services to the OSReal-mode interrupts: INT 13h for disks, INT 10h for videoBoot Services until the OS takes over, then Runtime Services
Verifies the loaderNoYes, with Secure Boot: db, dbx, KEK, PK
Hardware root of trustNone in the designIntel Boot Guard or AMD Platform Secure Boot, if the OEM fuses them

Sources: MBR (x86), Windows and GPT FAQ, EFI boot stub, PI boot flow.

Secure Boot keys

UEFI Secure Boot continues the chain past the firmware: four key databases decide which OS loader may run.

PK Platform Key
The platform owner's key, usually the OEM's. Only it can change the KEK. Enrolling a PK moves the firmware from setup mode, where Secure Boot is off, to user mode.
KEK Key Exchange Keys
Keys of OS vendors, such as Microsoft's KEK CA. They sign updates to db and dbx.
db Allowed signatures
Certificates and hashes of allowed images. PCs ship Microsoft's Windows CA, and its UEFI CA for third-party loaders such as shim.
dbx Forbidden signatures
Revoked certificates and hashes, checked before db: a match blocks the image.

Microsoft's 2011 certificates start expiring in June 2026: PCs need the 2023 CAs to keep receiving db and dbx updates. Source: Secure Boot key guidance.

Public Secure Boot breaks

  • BootHole (2020): A buffer overflow in GRUB's parser for grub.cfg, a file nobody signs, ran attacker code with Secure Boot on (CVE-2020-10713).
  • BlackLotus (2023): The first bootkit seen in the wild to bypass Secure Boot on fully patched Windows 11, by bringing old, validly signed but vulnerable boot managers that dbx did not yet block (CVE-2022-21894).
  • LogoFAIL (2023): Bugs in the image parsers that draw the boot logo during DXE let a crafted logo run code inside the firmware, on x86 and Arm devices.
  • PKfail (2024): Hundreds of PC models shipped AMI's test Platform Key, marked "DO NOT TRUST"; one such private key leaked, so anyone holding it could rewrite KEK and db.

// firmware --> kernel --> init

From the loader to the kernel

Arm and PC boots meet here: BL33 or the UEFI firmware hands over to an OS loader, which starts the kernel.

From the firmware to the real root filesystem, with the Secure Boot checksA row of six stages: the firmware (BL33 on Arm, UEFI on a PC), shim, GRUB or systemd-boot, the kernel, the initramfs, and the real root filesystem running systemd. Shim and GRUB form step 7, the OS loader; the kernel is step 8; the initramfs and the real root are step 9. Red arrows show the checks: the firmware checks shim against db and dbx, shim checks GRUB against the vendor certificate or a MOK, shim checks the kernel when GRUB asks it to, and dm-verity can check the real root. A dashed path shows the firmware starting the kernel directly, through the EFI stub or U-Boot with a signed FIT image. Below, the initramfs, command line and devicetree or ACPI tables are handed to the kernel, and the kernel checks the signature of every module it loads.7OS loader8Kernel entry9initramfs, then initFirmwareBL33 on Arm,UEFI on a PCshimsigned by Microsoft'sUEFI CAGRUBor systemd-boot;loads the kernelKernelMMU on, memory,starts other coresinitramfs/init is PID 1,finds the real rootReal root fsswitch_root, thensystemdchecks db, dbxvendor cert or MOKchecks the kernel when GRUB asksdm-verity, if usedor straight to the kernel: EFI stub, or U-Boot with a signed FIT imageHanded to the kernelinitramfs, command line,devicetree (Arm) or ACPI tables (PC)Kernel modulessignature checked on load,from the initramfs or the root fschecks the signature before it runs (with Secure Boot on)optional checkboot orderskips the OS loader
A Linux distribution under Secure Boot, on a PC or an Arm board with UEFI. Windows replaces shim and GRUB with its Boot Manager and winload, which check the kernel. Sources: shim, EFI boot stub, U-Boot FIT signature, module signing, dm-verity.

Kernel boot, step by step

  1. 7

    OS loader (EFI application). BL33, or the PC's UEFI firmware, runs an EFI application from the FAT EFI System Partition: shim and GRUB, systemd-boot or the Windows Boot Manager. With Secure Boot on, the firmware checks it against db and dbx first. It loads the kernel, an initramfs and the command line. Linux can skip this stage: with the EFI stub, the kernel image is itself a PE/COFF EFI application. U-Boot can also boot the kernel directly from a signed FIT image.

  2. 8

    Kernel entry. The loader also passes a description of the hardware: a devicetree on embedded boards, ACPI tables on PCs and Arm servers. On arm64 the kernel starts with the MMU off, the devicetree address in register x0, in non-secure EL2 (recommended, for virtualisation) or EL1. It builds its page tables, turns the MMU on, sets up memory, interrupts and the scheduler, and starts the other cores, on Arm through PSCI calls to BL31.

  3. 9

    initramfs, then init. The kernel unpacks the initramfs, a cpio archive, into a RAM filesystem and runs its /init as PID 1. This early userspace finds the real root filesystem, possibly unlocking it with a TPM-sealed key or checking it with dm-verity, then switches to it and runs the real init, usually systemd.

Numbers continue the TF-A steps 0 to 6. Sources: Booting AArch64 Linux, EFI boot stub, initramfs.

Linux under Secure Boot

Microsoft signs shim, a small first-stage loader, with its UEFI CA. shim carries the distribution's certificate and checks GRUB and the kernel against it, or against a Machine Owner Key (MOK) that the user enrolls. GRUB's config file is not signed, which is what BootHole exploited. Since then, shim checks SBAT generation numbers in signed metadata, so a vulnerable version can be revoked by number instead of filling dbx with hashes. With kernel lockdown on, which distributions usually enable under Secure Boot, the kernel loads only signed modules and also refuses /dev/mem, kexec of unsigned kernels and unencrypted hibernation.

// verify vs record

Secure boot vs measured boot

Two mechanisms run along the whole chain, from the root of trust to the kernel, on Arm and PCs alike. Secure boot (then trusted boot, in Windows terms) verifies each stage and stops on a bad signature. Measured boot hashes each stage into a TPM and never blocks, so a key store or a remote server can tell what actually ran.

Secure boot, trusted boot and measured boot on one boot chainA row of boot stages: BL1, BL2, BL31 and BL32, BL33, the OS loader and the kernel. Red arrows above the row show which stage verifies which: a root key hash anchors BL1, BL1 verifies BL2, BL2 verifies BL31, BL32 and BL33, BL33 verifies the OS loader (secure boot), and the OS loader verifies the kernel (Windows trusted boot). Indigo arrows below show BL1, BL2, BL33 and the OS loader hashing the next stage into a TPM, whose measurements feed local policy such as disk key unsealing and remote attestation.BL1Boot ROMBL2loads the restBL31 / BL32EL3 + secure OSBL33U-Boot or UEFIOS loaderbootmgr, GRUBKerneldrivers, ELAMRoot key hashOTP or ROMverifies BL2verifies BL31/32verifies BL33verifies OS loaderverifies kernelSecure boot (firmware; TF-A calls it Trusted Board Boot)Trusted boot (Windows)hashes BL2hashes BL3xhashes OS loaderhashes kernel, driversTPM / secure elementExtend-only PCRs: new PCR = hash(old PCR + measurement), plus an event log. Nothing is blocked.Local policyUnseal the disk key only if the PCRs matchRemote attestationA signed PCR quote tells a server what bootedverify: a bad signature stops the bootmeasure: record a hash, never blockboot order
Red arrows verify and can stop the boot. Indigo arrows only record. BL31 and BL32 verify nothing here and are measured by BL2; BL1 is the root of trust for measurement, so nothing measures it.
Secure + trusted bootMeasured boot
Doesverifies a signaturehashes the image, extends a PCR
On mismatchhalts or recoversboots on, the PCR differs
Answersmay this code run?what code did run?
Trust anchorkey hash in OTP or ROMimmutable ROM + TPM
Used forblocking unsigned codekey release, attestation

Naming. Windows splits verification in two: secure boot (UEFI checks the OS loader) and “trusted boot” (the OS loader checks the kernel, drivers and ELAM). TF-A’s “Trusted Board Boot” is the firmware half. Measured boot is separate: it records and never verifies, though some documents (Intel’s tboot) also call it “trusted boot”. TF-A builds both with TRUSTED_BOARD_BOOT=1 and MEASURED_BOOT=1. Sources: TF-A Measured Boot design, Windows boot process.